1. Field of the Invention
The present invention generally relates to the formation of integrated circuits, and, more particularly, to the fabrication of highly conductive metal features.
2. Description of the Related Art
In modern integrated circuits, a high number of individual circuit elements, such as transistors, capacitors, resistors and the like, are formed in and on an appropriate substrate, typically in a substantially planar arrangement. The electrical connections between the circuit elements may not be provided within the same level, as the number of connections is usually significantly higher than the number of circuit elements. Consequently, one or more wiring levels or layers are provided which include the metal lines and metal regions establishing the electrical connections within a specified level (considered as inner-level connections) and the vias connecting metal lines or regions in different levels (considered as inter-level connections). A wiring layer is typically referred to as a metallization layer, wherein, depending on terminology, a metallization layer may also be understood as containing one layer having formed therein the wires providing the inter-level to one adjacent metal line layer. Herein, a metallization layer comprises at least one of a metal line layer, i.e., inner-level connections, and a via layer, i.e., inter-level connections. The metallization layers, and in particular the metal features of a semiconductor device, may be considered as a wiring network having a lower end in the form of a metal line layer that comprises a complex structure to connect to respective contact plugs directly terminating at circuit elements and having an upper end in the form of a metal line layer of reduced complexity to provide the electrical connections to the periphery, that is, to a carrier substrate or a package. The wiring network with the intermediate metal line layers and via layers and the upper and lower contact ends thus provides the electrical connections in accordance with the electrical design of the one or more circuits provided in a respective chip.
While aluminum is a well-approved metal in the semiconductor industry, in modern integrated circuits, highly conductive metals, such as copper and alloys thereof, are increasingly used to accommodate the high current densities encountered during the operation of the devices, as the ongoing reduction of feature sizes also leads to reduced dimensions of the metal lines and vias. Consequently, the metal features may comprise metal lines and vias formed from copper or copper alloys.
Copper and copper-based alloys are attractive for use in semiconductor devices requiring multi-level metallization systems for back-end processing of the semiconductor wafers on which the devices are based. Copper and copper alloy based metallization systems have very low resistivities, i.e., significantly lower than that of tungsten and even lower than aluminum and its alloys. Further, copper and copper alloy based metallization systems have a high resistance to electromigration. In order to improve the electromigration behavior of the copper and copper alloy based metal features, it has been suggested to cover the surface of a respective metal feature with a cobalt-based, e.g., a cobalt tungsten phosphide (CoWP) or a cobalt tungsten boride (CoWB) capping layer. Moreover, copper and it's alloys can be readily deposited at low temperatures in good quality by well-known wet plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
Electroless plating of copper generally involves the controlled auto-catalytic deposition of a continuous film of copper or an alloy thereof on a catalytic surface by the incorporation of at least one copper-containing salt and a chemical reducing agent contained in a suitable solution. Electroplating comprises employing electrons supplied to an electrode which comprises the surface to be plated from an external source, e.g., a power supply, for reducing copper ions in solution and depositing reduced copper metal atoms on the plating surface. In either case, a nucleation/seed layer is required for catalyzes and/or deposition on the substrate. Finally, while electroplating requires continuous nucleation/seed layer, very thin and discontinuous islands of catalytic metal may be employed with electroless plating.
Since copper and copper based alloys are relatively difficult to etch, at least at low temperatures, copper wirings are typically formed as an “in-laid” metallization pattern by a so-called damascene technology. Generally, in damascene technology, a recess, e.g., a via hole in a dielectric layer for electrically connecting vertically separated metal features, or a groove or trench for a metal line, is created in a dielectric layer by conventional photolithographic and etching techniques, and filled with a selected material. Any excess metal overfilling the recess and/or extending over the surface of the dielectric layer is then removed by planarizing, e.g., chemical mechanical polishing (CMP), wherein a moving pad is biased against a surface to be polished/planarized with the interposition of an appropriate slurry therebetween.
A variant of the above-described single damascene technique involves the formation of an opening comprising a lower contact or a via hole section in communication with an upper groove or trench section. The opening is filled with a conductive material, typically a metal, to simultaneously form a conductive via plug in electrical contact with a conductive line. A process of this kind is referred to as a dual damascene process.
In a damascene process, at first the desired arrangement of conductors is defined as a pattern of recesses, such as via holes, grooves, trenches, etc., formed in a dielectric layer by conventional photolithographic and etching techniques. Subsequently, an adhesion promoting and/or diffusion barrier layer is formed in the recesses in the dielectric layer. Suitable materials for such an adhesion/barrier layer include, e.g., titanium, tungsten, chromium, tantalum and tantalum nitride.
With reference to FIG. 1, a typical conventional process flow will now be described to explain the principles of the damascene process in more detail. FIG. 1 schematically shows a semiconductor device 100 that is formed in accordance with a conventional technique, including a metallization layer stack on the basis of copper. The semiconductor device 100 comprises a substrate 101, which is to represent any appropriate substrate for the formation of circuit elements therein and thereon, wherein, for convenience, any such circuit elements are not shown. Formed above the substrate 101 are one or more metallization layers, including respective metal features, e.g., vias and metal lines, as is explained above. For clarity reasons, a portion of one metallization layer 110 is illustrated in FIG. 1, on which is formed a second metallization layer 120. The metallization layer 110 may comprise a metal line layer of which is shown a metal line 112 that is covered by a dielectric barrier and etch stop layer 111. For example, the metal line 112 may represent a copper-based metal line which is to be understood as a line in which a substantial portion is copper. It should be appreciated that other materials may be contained in the metal line 112, such as conductive barrier materials and the like, as well as other metals for forming a copper alloy, for instance at specific areas within the metal line 112, wherein it should be understood that, nevertheless, a significant amount, that is, more than approximately 50 atomic percent of the material of the line 112 is copper. The barrier and etch stop layer 111 may be comprised of any appropriate dielectric materials, such as silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like. The second metallization layer 120 may comprise a via layer 122 which may comprise an appropriate dielectric material 127, also referred to as interlayer dielectric material (ILD), in which is formed a via 113 that is substantially comprised of copper, wherein, for instance, a conductive barrier layer 125 may provide the required adhesion and diffusion blocking characteristics. Typical materials for the barrier layer 125 are tantalum, tantalum nitride, titanium, titanium nitride and the like. The last metallization layer 120 further comprises a further metal line layer 121 which may comprise an appropriate interlayer dielectric material, such as the material 127, which may be comprised of any appropriate materials, such as silicon dioxide, silicon nitride and the like. In sophisticated applications, the interlayer dielectric material of the metal line layer 121 may comprise a low-k dielectric material having a relative permittivity of 3.0 or even less. In the dielectric material 127 is formed a copper-based metal line 124, which may also be separated from the interlayer dielectric material 127 by a barrier layer 125.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1 may comprise the following processes. After the formation of any circuit elements and respective metallization layers, the metallization layer 110 may be formed on the basis of well-established single or dual damascene or inlaid techniques in which a dielectric layer may be deposited first and may be subsequently patterned to receive via openings or trenches which may then, commonly or separately, be filled with the copper-based material. For example, the metallization layer 110 may be formed by depositing an appropriate dielectric material, such as a low-k material, which is subsequently patterned to receive first vias and trenches or to receive first trenches and then vias, which are subsequently coated with an appropriate barrier material, wherein subsequently copper may be filled in by electroplating or any other appropriate deposition technique. In damascene regimes, a via layer may be formed first and subsequently the interlayer dielectric material may be deposited in an appropriate thickness to form therein trenches for receiving the metal line 112.
Thereafter, the barrier layer 111 may be formed on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques. Thereafter, the second metallization layer 120 may be formed. For convenience, in the following process flow, it may be assumed that the via layer 122 and the metal line layer 121 may be formed in accordance with a dual inlaid technique in which corresponding via openings are formed first and subsequently trenches are etched into the dielectric layer. Subsequently, the via opening and the trench are filled in a common process sequence. Consequently, the interlayer dielectric material 127 may be formed on the basis of any appropriate technique, such as PECVD, spin-on techniques, or any combination thereof, wherein, in some regimes, an intermediate etch stop layer may be provided to separate the via layer 122 from the metal line layer 121. In other approaches, the interlayer dielectric material 127 may be provided as a substantially continuous layer.
Thereafter, respective via openings may be formed throughout the entire layer 127 by providing a corresponding resist mask and etching through the layer 127, wherein the barrier etch stop layer 111 may be used to reliably stop the corresponding isotropic etch process. Thereafter a further resist mask may be formed and corresponding trenches may be etched into the layer 127 in accordance with dimensions required for the metal line 124. After removal of the resist mask and any other resist material or polymer material required for the second etch step, the etch stop layer 111 may be opened to connect the respective via opening with the underlying metal line 112. Thereafter, the barrier layer 125 may be formed and thereafter copper may be deposited into the respective structure, thereby forming the via 113 and the metal line 124 in a common deposition process. In order to ensure complete filling of the recess, the copper-containing layer is deposited as a blanket or overburden layer of excess thickness so as to overfill the recesses and cover the upper surface of the dielectric layer 127. The entire excess thickness of the metal overburden layer over the surface of the dielectric layer 127 is removed by a planarizing process, e.g., a CMP process, leaving metal portions in the recesses with their exposed upper surfaces substantially coplanar with the surface of the dielectric layer 127.
A drawback associated with the use of copper or copper-based metallurgy for metallization processes of semiconductor devices, e.g., back-end metallization processes, results from the undesirable formation of copper oxide on the planarized copper or copper-based surfaces of the inlaid metallization features as a result of oxidation, e.g., due to the strong chemical oxidizing agents conventionally included in CMP slurries for enhancing copper dissolution/removal rates or as a result of exposure of the freshly abraded copper-based surfaces to an oxidizing atmosphere, for instance, air or oxygen. The thickness of the copper oxide layer may vary depending on the particular CMP processing conditions, for instance, stronger oxidizing agents contained in the CMP slurry result in thicker oxide layers. In order to reduce the adverse effects of copper oxide, it has been proposed to deposit a metallic passivant element for passivating the copper surface and subsequently effecting reaction between the metallic passivant element and the copper surface to form a passivating layer, thereby improving the electromigration behavior of the respective copper line.
Electromigration occurs in extended runs or lengths of metal conductor lines carrying significant currents. According to a conventional theory for explaining the mechanism of electromigration, the current flow within the conductor line may be sufficient to result in movement of metal, for instance, copper, atoms and/or ions along the line by means of momentum transfer due to collision of the metal atoms and/or ions with energetic, flowing electrons. The current flow may also create a thermal gradient along the conductor length which increases the mobility of the metal atoms and/or ions. As a consequence of the momentum transfer and the thermally enhanced mobility, metal atoms and/or ions diffuse in the direction of the current flow and metal loss at the source end of the conductor eventually results in thinning of the conductor line. The electromigration effect may continue until the conductor line becomes so thin that it separates from the current input and forms an open circuit, resulting in failure of the integrated circuit. As this usually occurs over an extended period of operation, the failure is often seen by the end user.
The present disclosure is directed to various methods and systems that may avoid, or at least reduce, the effects of one or more of the problems identified above.